The present invention relates to semiconductor devices and, more particularly, to a high voltage generator in a semiconductor device, which can reduce the operating current during an active operation.
In general, the power supply of a semiconductor memory device can be classified into external power or internal power.
The external power would include Vext (external voltage), Vss (ground voltage), Vref (input reference voltage), VextQ (quiet external voltage) and so on. The internal power would include Vpp (word line enable voltage), Vbb (cell array bulk bias voltage), Vint (internal operating voltage) and the like.
Meanwhile, a cell block within most DRAM is designed to have one transistor and one cell capacitor coupled to each other. The cell transistor generally employs NMOS transistors due to their advantages in area and current driving ability. In order to read and write a logic high data from and into the cell, a voltage higher than the voltage of the data is applied to the gate of the cell transistor. The voltage for driving the cell transistor is usually called “high voltage Vpp”.
FIG. 1 is a circuit diagram of a conventional high voltage generator in a semiconductor device.
Referring to FIG. 1, the high voltage generator 10 of the semiconductor device includes a first high voltage pump unit 20, a second high voltage pump unit 30 and an oscillator 40.
The operation of the high voltage generator 10 of the semiconductor device is described by showing the generation of a first high voltage Vpp1 in an example below.
If an enable signal EN is activated according to timing stored in ROM in the semiconductor device, the oscillator 40 is enabled and generates the clock signals CLK1 and CLK2.
The high voltage Vpp1 output from the first high voltage pump unit 20 is divided by resistors R1 and R2. A comparator 22 compares a divided voltage Va, and a reference voltage Vref generated from a reference voltage generator 23, and generates a buffer enable signal en1.
A first buffer 24 is activated in response to the buffer enable signal en1, and outputs a pump enable signal P-en1 synchronized with the clock signal CLK1.
A first high voltage pump 21 boosts the high voltage Vpp1 to a specific voltage level in response to the pump enable signal P-en1.
FIG. 2 shows several waveform signals for illustrating the operation of FIG. 1.
Referring to FIG. 2, the high voltage generating device 10 of the semiconductor device continues to generate the clock signals CLK1 and CLK2 during an active operating time OP TIME of the device. The generated clock signals CLK1 and CLK2 are transferred to the high voltage pump units 20 and 30, and take part in the pumping operation. However, time at which the high voltage pump units 20 and 30 operate substantially is not a total active operating time OP TIME, but is an initial time of each operating mode, that is, an initial pumping time A of a program operation or an initial pumping time B of a read operation. Thus, the oscillator 40 is unnecessarily enabled during the active operating time OP TIME to generate the clock signals CLK1 and CLK2, so that power is wasted.